This invention will be described in the environment of audio signal processing apparatus, however its utility is not limited to this application. The only limitation on the type of signals that may be processed by the invention relates to the signal bandwidth and the availability of circuit elements having sufficient operating speeds.
It is known to process audio signals using digital circuitry. Typically, such circuitry converts analog audio signals to binary values, arithmetically manipulates the binary values with binary circuitry to perform filtering, tone and volume control functions etc., and then converts the processed binary values back into analog signals for sound reproduction. In order to minimize the circuitry for converting the analog signals to binary values sigma-delta modulators are often utilized. Normally sigma-delta modulators sample the audio signal at a rate which is orders of magnitude greater than the highest audio frequency present. The quantization of the signals provided by the sigma-delta modulator is relatively coarse. Typically the high rate, coarsely quantized samples are filtered and subsampled to create samples having significantly lower quantization error and a manageable sample rate. See for example the articles by James C. Candy entitled "Decimation For Sigma Delta Modulation", IEEE Transactions on Communications, Vol., COM-34, No. 1, Jan. 86, pp. 72-76 and "A Use of Double Integration In Sigma Delta Modulation", IEEE Transactions on Communications, Vol. COM-33, No. 3, March 1985, pp. 249-258 . The subsampled signals are processed at the lower rate and then reconverted to analog form. In order to minimize the circuitry for digital-to-analog conversion some such systems resample the processed binary values to a higher rate and to a very coarse quantization level, e.g., to two levels. The coarsely quantized, high rate samples are then integrated/averaged on a capacitor to generate the analog signal. The requantization is performed by a process of interpolation. See for example the article by James C. Candy et al. entitled "Double Interpolation For Digital-to-Analog Conversion, IEEE Transactions on Communications, Vo. COM-34, No. 1, January 1986, pp. 77-81. Interpolation of the type described by Candy et al. incorporates the process of accumulating each processed sample n times where n corresponds to the resampling factor. As such the accumulated values tend to become large requiring relatively large accumulators. In addition, if the binary values are processed in bit-serial format, significant speed constraints are imposed on the processing circuitry due to the high resample rate and the large accumulated values.
It is an object of the present invention to provide simplified digital-to-analog conversion apparatus which obviates processing large accumulated values in the interpolation process.
It is a further object of the invention to provide a bit-serial digital-to-analog converter which operates in pipelined fashion to minimize timing constraints on the overall system.